CWE-1209: Failure to Disable Reserved Bits

BaseIncomplete

The reserved bits in a hardware design are not disabled prior to production. Typically, reserved bits are used for future capabilities and should not support any functional logic in the design. However, designers might covertly use these bits to debug or further develop new capabilities in production hardware. Adversaries with access to these bits will write to them in hopes of compromising hardware state.

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Extended Description

Reserved bits are labeled as such so they can be allocated for a later purpose. They are not to do anything in the current design. However, designers might want to use these bits to debug or control/configure a future capability to help minimize time to market (TTM). If the logic being controlled by these bits is still enabled in production, an adversary could use the logic to induce unwanted/unsupported behavior in the hardware.

Code Examples & CVEs

Demonstrative Examples

Assume a hardware Intellectual Property (IP) has address space 0x0-0x0F for its configuration registers, with the last one labeled reserved (i.e. 0x0F). Therefore inside the Finite State Machine (FSM), the code is as follows:

An adversary may perform writes to reserved address space in hopes of changing the behavior of the hardware. In the code above, the GPIO pin should remain low for normal operation. However, it can be asserted by accessing the reserved address space (0x0F). This may be a concern if the GPIO state is being used as an indicator of health (e.g. if asserted the hardware may respond by shutting down or resetting the system, which may not be the correct action the system should perform). In the code below, the condition "register_address = 0X0F" is commented out, and a default is provided that will catch any values of register_address not explicitly accounted for and take no action with regards to gpio_out. This means that an attacker who is able to write 0X0F to register_address will not enable any undocumented "features" in the process.

BadVerilog

reg gpio_out = 0;  //gpio should remain low for normal operation                                              case (register_address) 		                               4'b1111 : //0x0F 			 			  begin 			                               gpio_out = 1; 			   			  end

GoodVerilog

reg gpio_out = 0;  //gpio should remain low for normal operation 			                     	  case (register_address) 			                     	    //4'b1111 : //0x0F                   	    default: gpio_out = gpio_out;

Source-backed guidance

Additional facts reviewed against primary or authoritative security sources.

Verify controls for CWE-1209 with SSDF evidence

Use NIST SSDF verification and vulnerability-response practices to detect CWE-1209, Failure to Disable Reserved Bits, throughout the product lifecycle. Derive review questions, static or dynamic checks, and negative tests from the CWE's causal behavior; define the components and lifecycle stages each check covers; and retain findings with enough evidence to distinguish the root cause from symptoms and impacts. Track escapes and false negatives, then improve the verification plan after every confirmed occurrence.

NIST SP 800-218 Secure Software Development Framework — National Institute of Standards and Technology

Address Failure to Disable Reserved Bits during Architecture and Design

MITRE associates mitigation with Architecture and Design, Implementation, and Integration; recorded impacts include Varies by Context; the entry maps to CAPEC-121. Use these source-defined anchors to turn CWE-1209 into implementation, review, and verification checks for the affected component.

CWE-1209: Failure to Disable Reserved Bits — MITRE CWE

Triage CWE-1209 against known exploitation evidence

Use CISA's Known Exploited Vulnerabilities catalog to test whether a vulnerability mapped to CWE-1209, Failure to Disable Reserved Bits, has evidence of exploitation in the wild. Confirm the CVE-to-CWE root-cause mapping independently before attaching the example, then capture the affected product, required action, and remediation deadline. A missing KEV match is not evidence that the weakness is unexploited, and a KEV entry must not be generalized to every occurrence of this CWE.

Known Exploited Vulnerabilities Catalog — Cybersecurity and Infrastructure Security Agency

Apply precise root-cause mapping to CWE-1209

Apply MITRE's full root-cause mapping guidance when using CWE-1209, Failure to Disable Reserved Bits. Separate weakness language from attacker prerequisites and technical impact, check the entry's abstraction and vulnerability-mapping notes, and prefer the most specific Base or Variant supported by the evidence. Record the rejected alternatives and require an independent review before the mapping is used for remediation trends or program metrics.

CVE to CWE Root Cause Mapping Guidance — MITRE CWE

Validate CWE-1209 with root-cause mapping checks

Apply MITRE's root-cause mapping quick tips to CWE-1209, Failure to Disable Reserved Bits. Confirm the finding describes the causal weakness rather than an impact or attack pattern, compare the abstraction and mapping notes with plausible alternatives, and have a second reviewer challenge the selection. Preserve the evidence and reasoning so recurring defects can be measured against one consistent identifier.

CVE to CWE Root Cause Mapping Quick Tips — MITRE CWE

Frequently Asked Questions

What is CWE-1209: Failure to Disable Reserved Bits?+

CWE-1209: Failure to Disable Reserved Bits is a Common Weakness Enumeration (CWE) entry maintained by MITRE. The reserved bits in a hardware design are not disabled prior to production. Typically, reserved bits are used for future capabilities and should not support any functional logic in the design. However, designers might covertly use these bits to debug or further develop new capabilities in production hardware. Adversaries with access to these bits will write to them in hopes of compromising hardware state. Reserved bits are labeled as such so they can be allocated for a later purpose. They are not to do anything in the current design. However, designers might want to use these bits to debug or control/configure a future capability to help minimize time to market (TTM). If the logic being controlled by these bits is still enabled in production, an adversary could use the logic to induce unwanted/unsupported behavior in the hardware.

What are the security consequences of Failure to Disable Reserved Bits?+

If exploited, CWE-1209 (Failure to Disable Reserved Bits) it can compromise Confidentiality, Integrity, Availability, Access Control, Accountability and Authentication, leading to outcomes such as Varies by Context.

How do you prevent or mitigate Failure to Disable Reserved Bits?+

Recommended mitigations for CWE-1209 include: Include a feature to disable reserved bits. Any writes to these reserve bits are blocked (e.g., ignored, access-protected, etc.), or an exception can be asserted.

Which programming languages are affected by Failure to Disable Reserved Bits?+

CWE-1209 commonly affects Not Language-Specific. Note that weaknesses are often language-agnostic patterns, so secure coding practices apply broadly.

What is the difference between a CWE and a CVE?+

A CWE (Common Weakness Enumeration) like CWE-1209 describes a category of software weakness — the underlying flaw type. A CVE (Common Vulnerabilities and Exposures) identifies a specific, real-world vulnerability in a particular product. In short, a CWE is the kind of mistake, and a CVE is an instance of that mistake being found in software.

CWE-1209: Failure to Disable Reserved Bits

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