CWE-1239: Improper Zeroization of Hardware Register

Extended Description

Hardware logic operates on data stored in registers local to the hardware block. Most hardware IPs, including cryptographic accelerators, rely on registers to buffer I/O, store intermediate values, and interface with software. The result of this is that sensitive information, such as passwords or encryption keys, can exist in locations not transparent to the user of the hardware logic. When a different entity obtains access to the IP due to a change in operating mode or conditions, the new entity can extract information belonging to the previous user if no mechanisms are in place to clear register contents. It is important to clear information stored in the hardware if a physical attack on the product is detected, or if the user of the hardware block changes. The process of clearing register contents in a hardware IP is referred to as zeroization in standards for cryptographic hardware modules such as FIPS-140-2 [REF-267].

Code Examples & CVEs

Demonstrative Examples

The example code below [REF-1379] is taken from the SHA256 Interface/wrapper controller module of the HACK@DAC'21 buggy OpenPiton SoC. Within the wrapper module there are a set of 16 memory-mapped registers referenced data[0] to data[15]. These registers are 32 bits in size and are used to store the data received on the AXI Lite interface for hashing. Once both the message to be hashed and a request to start the hash computation are received, the values of these registers will be forwarded to the underlying SHA256 module for processing. Once forwarded, the values in these registers no longer need to be retained. In fact, if not cleared or overwritten, these sensitive values can be read over the AXI Lite interface, potentially compromising any previously confidential data stored therein.

In the previous code snippet [REF-1379] there is the lack of a data clearance mechanism for the memory-mapped I/O registers after their utilization. These registers get cleared only when a reset condition is met. This condition is met when either the global negative-edge reset input signal (rst_ni) or the dedicated reset input signal for SHA256 peripheral (rst_3) is active. In other words, if either of these reset signals is true, the registers will be cleared. However, in cases where there is not a reset condition these registers retain their values until the next hash operation. It is during the time between an old hash operation and a new hash operation that that data is open to unauthorized disclosure.

BadVerilog

... 						 						// Implement SHA256 I/O memory map interface 						// Write side 						always @(posedge clk_i) 							 							begin 								 								if(~(rst_ni && ~rst_3)) 									 									begin 										 										startHash <= 0; 										newMessage <= 0; 										data[0] <= 0; 										data[1] <= 0; 										data[2] <= 0; 										... 										data[14] <= 0; 										data[15] <= 0; 										 									 								 							 						 					...

GoodVerilog

... 						 						// Implement SHA256 I/O memory map interface 						// Write side 						always @(posedge clk_i) 							 							begin 								 								if(~(rst_ni && ~rst_3)) 									 									begin 										 										startHash <= 0; 										newMessage <= 0; 										data[0] <= 0; 										data[1] <= 0; 										data[2] <= 0; 										... 										data[14] <= 0; 										data[15] <= 0; 										 									end 									 								else if(hashValid && ~hashValid_r) 									 									begin 										 										data[0] <= 0; 										data[1] <= 0; 										data[2] <= 0; 										... 										data[14] <= 0; 										data[15] <= 0; 										 									end 									 								 							 						 					...

Source-backed guidance

Additional facts reviewed against primary or authoritative security sources.

Verify controls for CWE-1239 with SSDF evidence

Use NIST SSDF verification and vulnerability-response practices to detect CWE-1239, Improper Zeroization of Hardware Register, throughout the product lifecycle. Derive review questions, static or dynamic checks, and negative tests from the CWE's causal behavior; define the components and lifecycle stages each check covers; and retain findings with enough evidence to distinguish the root cause from symptoms and impacts. Track escapes and false negatives, then improve the verification plan after every confirmed occurrence.

NIST SP 800-218 Secure Software Development Framework — National Institute of Standards and Technology

Address Improper Zeroization of Hardware Register during Architecture and Design

MITRE associates mitigation with Architecture and Design; recorded impacts include Varies by Context; the entry maps to CAPEC-150, CAPEC-204, CAPEC-37, and CAPEC-545. Use these source-defined anchors to turn CWE-1239 into implementation, review, and verification checks for the affected component.

CWE-1239: Improper Zeroization of Hardware Register — MITRE CWE

Triage CWE-1239 against known exploitation evidence

Use CISA's Known Exploited Vulnerabilities catalog to test whether a vulnerability mapped to CWE-1239, Improper Zeroization of Hardware Register, has evidence of exploitation in the wild. Confirm the CVE-to-CWE root-cause mapping independently before attaching the example, then capture the affected product, required action, and remediation deadline. A missing KEV match is not evidence that the weakness is unexploited, and a KEV entry must not be generalized to every occurrence of this CWE.

Known Exploited Vulnerabilities Catalog — Cybersecurity and Infrastructure Security Agency

Apply precise root-cause mapping to CWE-1239

Apply MITRE's full root-cause mapping guidance when using CWE-1239, Improper Zeroization of Hardware Register. Separate weakness language from attacker prerequisites and technical impact, check the entry's abstraction and vulnerability-mapping notes, and prefer the most specific Base or Variant supported by the evidence. Record the rejected alternatives and require an independent review before the mapping is used for remediation trends or program metrics.

CVE to CWE Root Cause Mapping Guidance — MITRE CWE

Validate CWE-1239 with root-cause mapping checks

Apply MITRE's root-cause mapping quick tips to CWE-1239, Improper Zeroization of Hardware Register. Confirm the finding describes the causal weakness rather than an impact or attack pattern, compare the abstraction and mapping notes with plausible alternatives, and have a second reviewer challenge the selection. Preserve the evidence and reasoning so recurring defects can be measured against one consistent identifier.

CVE to CWE Root Cause Mapping Quick Tips — MITRE CWE

Frequently Asked Questions

What is CWE-1239: Improper Zeroization of Hardware Register?+

CWE-1239: Improper Zeroization of Hardware Register is a Common Weakness Enumeration (CWE) entry maintained by MITRE. The hardware product does not properly clear sensitive information from built-in registers when the user of the hardware block changes. Hardware logic operates on data stored in registers local to the hardware block. Most hardware IPs, including cryptographic accelerators, rely on registers to buffer I/O, store intermediate values, and interface with software. The result of this is that sensitive information, such as passwords or encryption keys, can exist in locations not transparent to the user of the hardware logic. When a different entity obtains access to the IP due to a change in operating mode or conditions, the new entity can extract information belonging to the previous user if no mechanisms are in place to clear register contents. It is important to clear information stored in the hardware if a physical attack on the product is detected, or if the user of the hardware block changes. The process of clearing register contents in a hardware IP is referred to as zeroization in standards for cryptographic hardware modules such as FIPS-140-2 [REF-267].

What are the security consequences of Improper Zeroization of Hardware Register?+

If exploited, CWE-1239 (Improper Zeroization of Hardware Register) it can compromise Confidentiality, leading to outcomes such as Varies by Context.

How do you prevent or mitigate Improper Zeroization of Hardware Register?+

Recommended mitigations for CWE-1239 include: Every register potentially containing sensitive information must have a policy specifying how and when information is cleared, in addition to clarifying if it is the responsibility of the hardware logic or IP user to initiate the zeroization procedure at the appropriate time.

Which programming languages are affected by Improper Zeroization of Hardware Register?+

CWE-1239 commonly affects Not Language-Specific. Note that weaknesses are often language-agnostic patterns, so secure coding practices apply broadly.

What is the difference between a CWE and a CVE?+

A CWE (Common Weakness Enumeration) like CWE-1239 describes a category of software weakness — the underlying flaw type. A CVE (Common Vulnerabilities and Exposures) identifies a specific, real-world vulnerability in a particular product. In short, a CWE is the kind of mistake, and a CVE is an instance of that mistake being found in software.

CWE-1239: Improper Zeroization of Hardware Register

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