CWE-1264: Hardware Logic with Insecure De-Synchronization between Control and Data Channels

Extended Description

Many high-performance on-chip bus protocols and processor data-paths employ separate channels for control and data to increase parallelism and maximize throughput. Bugs in the hardware logic that handle errors and security checks can make it possible for data to be forwarded before the completion of the security checks. If the data can propagate to a location in the hardware observable to an attacker, loss of data confidentiality can occur. 'Meltdown' is a concrete example of how de-synchronization between data and permissions checking logic can violate confidentiality requirements. Data loaded from a page marked as privileged was returned to the CPU regardless of current privilege level for performance reasons. The assumption was that the CPU could later remove all traces of this data during the handling of the illegal memory access exception, but this assumption was proven false as traces of the secret data were not removed from the microarchitectural state.

Code Examples & CVEs

Demonstrative Examples

There are several standard on-chip bus protocols used in modern SoCs to allow communication between components. There are a wide variety of commercially available hardware IP implementing the interconnect logic for these protocols. A bus connects components which initiate/request communications such as processors and DMA controllers (bus masters) with peripherals which respond to requests. In a typical system, the privilege level or security designation of the bus master along with the intended functionality of each peripheral determine the security policy specifying which specific bus masters can access specific peripherals. This security policy (commonly referred to as a bus firewall) can be enforced using separate IP/logic from the actual interconnect responsible for the data routing.

BadOther

The firewall and data routing logic becomes de-synchronized due to a hardware logic bug allowing components that should not be allowed to communicate to share data. For example, consider an SoC with two processors. One is being used as a root of trust and can access a cryptographic key storage peripheral. The other processor (application cpu) may run potentially untrusted code and should not access the key store. If the application cpu can issue a read request to the key store which is not blocked due to de-synchronization of data routing and the bus firewall, disclosure of cryptographic keys is possible.

GoodOther

All data is correctly buffered inside the interconnect until the firewall has determined that the endpoint is allowed to receive the data.

Observed CVE Examples (1)

CVE-2017-5754

Systems with microprocessors utilizing speculative execution and indirect branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis of the data cache.

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Source-backed guidance

Additional facts reviewed against primary or authoritative security sources.

Verify controls for CWE-1264 with SSDF evidence

Use NIST SSDF verification and vulnerability-response practices to detect CWE-1264, Hardware Logic with Insecure De-Synchronization between Control and Data Channels, throughout the product lifecycle. Derive review questions, static or dynamic checks, and negative tests from the CWE's causal behavior; define the components and lifecycle stages each check covers; and retain findings with enough evidence to distinguish the root cause from symptoms and impacts. Track escapes and false negatives, then improve the verification plan after every confirmed occurrence.

NIST SP 800-218 Secure Software Development Framework — National Institute of Standards and Technology

Address Hardware Logic with Insecure De-Synchronization between Control and Data Channels during Architecture and Design

MITRE associates mitigation with Architecture and Design; recorded impacts include Read Memory, and Read Application Data; the entry maps to CAPEC-233, and CAPEC-663. Use these source-defined anchors to turn CWE-1264 into implementation, review, and verification checks for the affected component.

CWE-1264: Hardware Logic with Insecure De-Synchronization between Control and Data Channels — MITRE CWE

Triage CWE-1264 against known exploitation evidence

Use CISA's Known Exploited Vulnerabilities catalog to test whether a vulnerability mapped to CWE-1264, Hardware Logic with Insecure De-Synchronization between Control and Data Channels, has evidence of exploitation in the wild. Confirm the CVE-to-CWE root-cause mapping independently before attaching the example, then capture the affected product, required action, and remediation deadline. A missing KEV match is not evidence that the weakness is unexploited, and a KEV entry must not be generalized to every occurrence of this CWE.

Known Exploited Vulnerabilities Catalog — Cybersecurity and Infrastructure Security Agency

Apply precise root-cause mapping to CWE-1264

Apply MITRE's full root-cause mapping guidance when using CWE-1264, Hardware Logic with Insecure De-Synchronization between Control and Data Channels. Separate weakness language from attacker prerequisites and technical impact, check the entry's abstraction and vulnerability-mapping notes, and prefer the most specific Base or Variant supported by the evidence. Record the rejected alternatives and require an independent review before the mapping is used for remediation trends or program metrics.

CVE to CWE Root Cause Mapping Guidance — MITRE CWE

Validate CWE-1264 with root-cause mapping checks

Apply MITRE's root-cause mapping quick tips to CWE-1264, Hardware Logic with Insecure De-Synchronization between Control and Data Channels. Confirm the finding describes the causal weakness rather than an impact or attack pattern, compare the abstraction and mapping notes with plausible alternatives, and have a second reviewer challenge the selection. Preserve the evidence and reasoning so recurring defects can be measured against one consistent identifier.

CVE to CWE Root Cause Mapping Quick Tips — MITRE CWE

Frequently Asked Questions

What is CWE-1264: Hardware Logic with Insecure De-Synchronization between Control and Data Channels?+

CWE-1264: Hardware Logic with Insecure De-Synchronization between Control and Data Channels is a Common Weakness Enumeration (CWE) entry maintained by MITRE. The hardware logic for error handling and security checks can incorrectly forward data before the security check is complete. Many high-performance on-chip bus protocols and processor data-paths employ separate channels for control and data to increase parallelism and maximize throughput. Bugs in the hardware logic that handle errors and security checks can make it possible for data to be forwarded before the completion of the security checks. If the data can propagate to a location in the hardware observable to an attacker, loss of data confidentiality can occur. 'Meltdown' is a concrete example of how de-synchronization between data and permissions checking logic can violate confidentiality requirements. Data loaded from a page marked as privileged was returned to the CPU regardless of current privilege level for performance reasons. The assumption was that the CPU could later remove all traces of this data during the handling of the illegal memory access exception, but this assumption was proven false as traces of the secret data were not removed from the microarchitectural state.

What are the security consequences of Hardware Logic with Insecure De-Synchronization between Control and Data Channels?+

If exploited, CWE-1264 (Hardware Logic with Insecure De-Synchronization between Control and Data Channels) it can compromise Confidentiality, leading to outcomes such as Read Memory and Read Application Data.

How do you prevent or mitigate Hardware Logic with Insecure De-Synchronization between Control and Data Channels?+

Recommended mitigations for CWE-1264 include: Thoroughly verify the data routing logic to ensure that any error handling or security checks effectively block illegal dataflows.

Which programming languages are affected by Hardware Logic with Insecure De-Synchronization between Control and Data Channels?+

CWE-1264 commonly affects Not Language-Specific. Note that weaknesses are often language-agnostic patterns, so secure coding practices apply broadly.

What are real-world examples of Hardware Logic with Insecure De-Synchronization between Control and Data Channels?+

MITRE documents real CVEs mapped to CWE-1264, including CVE-2017-5754. You can look up the full details of each CVE, including CVSS scores and remediation guidance, on our CVE Lookup tool.

What is the difference between a CWE and a CVE?+

A CWE (Common Weakness Enumeration) like CWE-1264 describes a category of software weakness — the underlying flaw type. A CVE (Common Vulnerabilities and Exposures) identifies a specific, real-world vulnerability in a particular product. In short, a CWE is the kind of mistake, and a CVE is an instance of that mistake being found in software.

CWE-1264: Hardware Logic with Insecure De-Synchronization between Control and Data Channels

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