CWE-1342: Information Exposure through Microarchitectural State after Transient Execution

Extended Description

In many processor architectures an exception, mis-speculation, or microcode assist results in a flush operation to clear results that are no longer required. This action prevents these results from influencing architectural state that is intended to be visible from software. However, traces of this transient execution may remain in microarchitectural buffers, resulting in a change in microarchitectural state that can expose sensitive information to an attacker using side-channel analysis. For example, Load Value Injection (LVI) [REF-1202] can exploit direct injection of erroneous values into intermediate load and store buffers. Several conditions may need to be fulfilled for a successful attack: incorrect transient execution that results in remanence of sensitive information; attacker has the ability to provoke microarchitectural exceptions; operations and structures in victim code that can be exploited must be identified.

Code Examples & CVEs

Demonstrative Examples

Faulting loads in a victim domain may trigger incorrect transient forwarding, which leaves secret-dependent traces in the microarchitectural state. Consider this example from [REF-1203].

Consider the code gadget:

BadC

void call_victim(size_t untrusted_arg) { 					     					      *arg_copy = untrusted_arg; 					      array[**trusted_ptr * 4096]; 					     					    }

Observed CVE Examples (1)

CVE-2020-0551

Load value injection in some processors utilizing speculative execution may allow an authenticated user to enable information disclosure via a side-channel with local access.

View Details

Source-backed guidance

Additional facts reviewed against primary or authoritative security sources.

Verify controls for CWE-1342 with SSDF evidence

Use NIST SSDF verification and vulnerability-response practices to detect CWE-1342, Information Exposure through Microarchitectural State after Transient Execution, throughout the product lifecycle. Derive review questions, static or dynamic checks, and negative tests from the CWE's causal behavior; define the components and lifecycle stages each check covers; and retain findings with enough evidence to distinguish the root cause from symptoms and impacts. Track escapes and false negatives, then improve the verification plan after every confirmed occurrence.

NIST SP 800-218 Secure Software Development Framework — National Institute of Standards and Technology

Address Information Exposure through Microarchitectural State after Transient Execution during Architecture and Design

MITRE associates mitigation with Architecture and Design, Requirements, and Build and Compilation; recorded impacts include Modify Memory, Read Memory, and Execute Unauthorized Code or Commands; the entry maps to CAPEC-696. Use these source-defined anchors to turn CWE-1342 into implementation, review, and verification checks for the affected component.

CWE-1342: Information Exposure through Microarchitectural State after Transient Execution — MITRE CWE

Triage CWE-1342 against known exploitation evidence

Use CISA's Known Exploited Vulnerabilities catalog to test whether a vulnerability mapped to CWE-1342, Information Exposure through Microarchitectural State after Transient Execution, has evidence of exploitation in the wild. Confirm the CVE-to-CWE root-cause mapping independently before attaching the example, then capture the affected product, required action, and remediation deadline. A missing KEV match is not evidence that the weakness is unexploited, and a KEV entry must not be generalized to every occurrence of this CWE.

Known Exploited Vulnerabilities Catalog — Cybersecurity and Infrastructure Security Agency

Apply precise root-cause mapping to CWE-1342

Apply MITRE's full root-cause mapping guidance when using CWE-1342, Information Exposure through Microarchitectural State after Transient Execution. Separate weakness language from attacker prerequisites and technical impact, check the entry's abstraction and vulnerability-mapping notes, and prefer the most specific Base or Variant supported by the evidence. Record the rejected alternatives and require an independent review before the mapping is used for remediation trends or program metrics.

CVE to CWE Root Cause Mapping Guidance — MITRE CWE

Validate CWE-1342 with root-cause mapping checks

Apply MITRE's root-cause mapping quick tips to CWE-1342, Information Exposure through Microarchitectural State after Transient Execution. Confirm the finding describes the causal weakness rather than an impact or attack pattern, compare the abstraction and mapping notes with plausible alternatives, and have a second reviewer challenge the selection. Preserve the evidence and reasoning so recurring defects can be measured against one consistent identifier.

CVE to CWE Root Cause Mapping Quick Tips — MITRE CWE

Frequently Asked Questions

What is CWE-1342: Information Exposure through Microarchitectural State after Transient Execution?+

CWE-1342: Information Exposure through Microarchitectural State after Transient Execution is a Common Weakness Enumeration (CWE) entry maintained by MITRE. The processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution. In many processor architectures an exception, mis-speculation, or microcode assist results in a flush operation to clear results that are no longer required. This action prevents these results from influencing architectural state that is intended to be visible from software. However, traces of this transient execution may remain in microarchitectural buffers, resulting in a change in microarchitectural state that can expose sensitive information to an attacker using side-channel analysis. For example, Load Value Injection (LVI) [REF-1202] can exploit direct injection of erroneous values into intermediate load and store buffers. Several conditions may need to be fulfilled for a successful attack: incorrect transient execution that results in remanence of sensitive information; attacker has the ability to provoke microarchitectural exceptions; operations and structures in victim code that can be exploited must be identified.

What are the security consequences of Information Exposure through Microarchitectural State after Transient Execution?+

If exploited, CWE-1342 (Information Exposure through Microarchitectural State after Transient Execution) it can compromise Confidentiality and Integrity, leading to outcomes such as Modify Memory, Read Memory and Execute Unauthorized Code or Commands.

How do you prevent or mitigate Information Exposure through Microarchitectural State after Transient Execution?+

Recommended mitigations for CWE-1342 include: Hardware ensures that no illegal data flows from faulting micro-ops exists at the microarchitectural level. Include instructions that explicitly remove traces of unneeded computations from software interactions with microarchitectural elements e.g. lfence, sfence, mfence, clflush.

Which programming languages are affected by Information Exposure through Microarchitectural State after Transient Execution?+

CWE-1342 commonly affects Not Language-Specific. Note that weaknesses are often language-agnostic patterns, so secure coding practices apply broadly.

What are real-world examples of Information Exposure through Microarchitectural State after Transient Execution?+

MITRE documents real CVEs mapped to CWE-1342, including CVE-2020-0551. You can look up the full details of each CVE, including CVSS scores and remediation guidance, on our CVE Lookup tool.

What is the difference between a CWE and a CVE?+

A CWE (Common Weakness Enumeration) like CWE-1342 describes a category of software weakness — the underlying flaw type. A CVE (Common Vulnerabilities and Exposures) identifies a specific, real-world vulnerability in a particular product. In short, a CWE is the kind of mistake, and a CVE is an instance of that mistake being found in software.

CWE-1342: Information Exposure through Microarchitectural State after Transient Execution

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